In recent years, a frame interline transfer type charge coupled device (hereinafter referred to as FIT-CCD) has been used in cameras for broadcasting and the like because it introduces small smear. Recently, attention has come to be given to progressive scan as a new picture format, and for implementing it, a solid-state image sensing device of multiple frame interline transfer type CCD (hereinafter referred to as MFIT-CCD) has been developed.
MFIT-CCD is disclosed in ISSCC Digest of Technical Papers, pp. 190–191 (1993).
MFIT-CCD has a characteristic feature that it not only achieves conventional interlace scan but also achieves progressive scan.
When pictures of a bright image objects are taken by a progressive scanning camera which employs such MFIT-CCD, outputs of pixels corresponding to even-numbered scanning lines (hereinafter referred to as even-numbered pixels) are saturated before pixels corresponding to odd-numbered scanning lines (hereinafter referred to as odd-numbered pixels) are saturated. Then, the outputs of the odd-numbered pixels become larger than that of the even-numbered pixels. This phenomenon occurs when scanning is made in the order of odd-numbered pixels first and then even-numbered pixels next. If the order is reversed, the result is inverted. Consequently, the phenomenon results in a difference in output level, namely, a difference in brightness of the picture picked up between odd-numbered pixels and even-numbered pixels, and hence it results in horizontal stripes in a picture, so as to degrade the picture quality.
First, such a phenomenon to degrade the picture quality in the prior art will be described in detail.
FIG. 9 is a block diagram showing an internal structure of MFIT-CCD. MFIT-CCD 60 is an image sensor disposed on a semiconductor substrate and comprises (1) pixel portion 65 formed of a group of photoelectric converters, e.g. photodiodes (hereinafter called PD group) 61, arranged in two dimensions, i.e. horizontal and vertical arrangement and CCD 62 for transferring charges in the vertical direction (hereinafter called VCCD 62), (2) CCD 63 for transferring charges in the horizontal direction (hereinafter called HCCD 63), (3) output amplifier 64, and (4) dummy portion 70. First charge memories 66 and second charge memories 67 do not include PD group and are equivalent to VCCD 62 which is photo-shielded.
In pixel portion 65, vertical transfer pulses φV1 –φV4 read charges obtained by photoelectric conversion in PD group 61, and feed the charges to VCCD 62, and then transfer the charges to charge memories 66 and 67 sequentially. Further, vertical transfer pulses φS1 –φS4 transfer the charges stored in charge memories 66 and 67 to HCCD 63. Horizontal transfer pulses φH1 and φH2 transfer the charges in HCCD 63 to output amplifier 64. Vertical transfer pulses φV1 –φV4 and φS1 –φS4 allow to change potential under the gate electrode (hereinafter called “gate”) of VCCD 62, made of poly-silicon or the like, so that charges are transferred vertically. Horizontal transfer pulses φH1 and φH2 allow to change potential under the gate electrode (hereinafter called “gate”) of HCCD 63 so that charges are transferred horizontally.
First, in pixel portion 65 of MFIT-CCD, a first transfer signal transfers charges of the odd-numbered pixels of PD group 61 to VCCD 62. Then, vertical transfer pulses φV1 –φV4 vertically transfer the charges of the odd-numbered pixels to charge memories 66. Next, a second transfer signal similarly transfers charges of the even-numbered pixels of PD group 61 to VCCD 62. Thereafter, the transfer signals vertically transfer the charges of odd-numbered pixels stored in charge memories 66 to charge memories 67 and then vertically transfer the charges of even-numbered pixels retained in VCCD 62 to charge memories 66.
Vertical transfer pulses φS1 –φS4 vertically transfer the charges of the odd-numbered pixels stored in charge memories 67 to HCCD 63 and, then, horizontal transfer pulses φH1 and φH2 horizontally transfer those charges to output amplifier 64. Further, vertical transfer pulses φS1 and φS4 vertically transfer the charges of the even-numbered pixels stored in charge memories 66 to charge memories 67 and then vertically transfer those charges to HCCD 63. Horizontal transfer pulses φH1 and φH2 at the next period horizontally transfer the charges of the even-numbered pixels stored in HCCD 63 to output amplifier 64. Thus, the transfer pulses transfer the charges of even-numbered pixels after the charges of odd-numbered pixels have all been transferred to output amplifier 64. Incidentally, similar things occur even if the transfer order of charges is changed in reverse order between odd-numbered pixels and even-numbered pixels.
Output amplifier 64 converts charges into voltage signals and supplies them to preamplifier 68 provided outside MFIT-CCD 60. Preamplifier 68 amplifies these voltage signals, eliminates noises therefrom, and makes analog-to-digital conversion of the signals. The output of preamplifier 68 is transmitted to rearranging circuit 69. Rearranging circuit 69 rearranges charge signals corresponding to odd-numbered pixels (n−1, . . . , 3, 1) and even-numbered pixels (n, . . . , 4, 2) in order of integers (n, n−1, . . . , 4, 3, 2, 1) and supplies these rearranged charge signal to a signal processing circuit in the succeeding stage. The signal processing circuit (not shown) processes the input signals by means of a γ-processing and a knee processing, and then produce voltage signals corresponding to the pixels.
FIG. 10 is a driving timing chart of MFIT-CCD. The first signal in the vertical blanking interval (hereinafter called “VBI”) shown in FIG. 10(a) sweeps out undesired charges. Thereafter, the transfer pulses at voltage VH shown in FIG. 10(b) simultaneously transfer the charges of the odd-numbered pixels and after then that of the even-numbered pixels to VCCD 62, respectively. Vertical transfer pulses at voltage VM (VM<VH) transfer the charges to charge memories 66 and 67 at high speed by means of time compression.
FIG. 11 and FIG. 12 are readout timing charts of MFIT-CCD. FIG. 11 shows timing at interlace scan and FIG. 12 shows timing at progressive scan. To explain the operations in more detail, portions of PD group 61 are illustrated as photodiodes P71, P72, and P73. The gates of VCCD 62 shown in FIG. 11(b) and FIG. 12(b) are made of poly-silicon as described above. Taking two adjoining photodiodes as one set, vertical transfer pulses φV1 –φV4 are supplied to the gates thereof. FIG. 11(c) shows potentials of the respective gates of VCCD 62 at time periods t1 –t4, in which the hatched portions illustrate the charges on pixels. When these charges are to be transferred from photodiodes to VCCD, in general, the pulse at voltage VH as shown in FIG. 10(b) is applied to the gate of φV1. Time period t1 in FIG. 11(c) shows the state of the charges transferred in this way from photodiodes P71 and P73 to the gates of φV1 of VCCD 62. Further, when the pulse at voltage VH is applied to the gate of φV3, the charge signal is transferred from photodiodes P72 and P74 (not shown) to the gates of φV3 of VCCD 62 as shown at time period t2 in FIG. 11 (c).
In the case of interlace scan, the gate of φV2 is turned on as shown at time period t3 in FIG. 11(c), so that the charges of photodiodes P71 and P72 are added together. Likewise, charges of photodiodes P73 and P74 are added together. Then, the added charges are collected under the gate electrodes to which φV2 and φV3 are applied as shown at time period t4 in FIG. 11(c). Thereafter, VCCD 62 alternately cycles the state at time period t3 and the state at time period t4 and, as a consequence, allows the charges to be transferred looking as if a measuring worm advances.
In the case of progressive scan as shown in FIG. 12, operations up to the time period t′1 in FIG. 12(c) are the same as in the case of interlace scan. In the case of progressive scan, however, charges are transferred through the time period t′2 after the charges of odd-numbered pixels have been read out. After the charges of the odd-numbered pixels have all been transferred, charges of even-numbered pixels (for example, those of photodiode P72) are read out, as shown at the time period t″1 in FIG. 12(c), and they are transferred through the state at the time period t″2.
With the conventional progressive scan as described above, there are some problems. FIG. 13 shows output signal levels of MFIT-CCD attained when readout was made as shown in FIG. 12. FIG. 13(a) shows output signal levels obtained from a low brightness image object, and FIG. 13(b) shows output signal levels obtained from a high-brightness object. In the case of a low-brightness image object, there is no level difference in the CCD output signals between odd-numbered pixels and even-numbered pixels. In the case of high-brightness image object, however, the output signal of even-numbered pixels saturate earlier and, hence, the output signal of odd-numbered pixels becomes larger than that of even-numbered pixels. When the readout order of odd-numbered pixels and even-numbered pixels are reversed, inverted phenomena occur.
More particularly, as shown in FIG. 13(b), the saturation voltage of the pixels read out first (odd-numbered pixels, in this case) becomes higher and the saturation voltage of the pixels read out secondly (even-numbered pixels, in this case) becomes lower.
Although this is a matter of presumption, it is supposed that, when first pixels are read out, a portion of signal charges stored in the pixels (photodiodes) to be read out at the next timing flow out into the semiconductor substrate side. Consequently, the saturation voltage of the pixels first read out becomes higher than the saturation voltage of the pixels read out secondly.
The output signals corresponding to odd-numbered pixels and even-numbered pixels are rearranged by rearranging circuit 69 in ascending order of integer as shown in FIG. 9. Consequently, when an image of high-brightness image object was picked up by MFIT-CCD, the above described phenomena cause a difference in reference levels and then in the output signal level between odd-numbered pixels and even-numbered pixels. Thus, a brightness difference is produced in the picture picked up between odd-numbered scanning lines and even-numbered scanning lines and, hence, many horizontal stripes are produced in one frame of picture to degrade the quality of the image. This is the first problem with the conventional art.
A second problem results from the structure of MFIT-CCD and it arises when charges are read out from dummy portion 70 shown in FIG. 9. FIG. 14 is an explanatory drawing of readout timing at boundary portions between constituents of MFIT-CCD. FIG. 14(a) shows the boundary portion between dummy portion 70 and pixel portion 65 and their potentials in relation with potential of VCCD 62. FIG. 14(b) shows the boundary portion between pixel portion 65 and charge memories 66 and their potentials in relation with potential of VCCD 62. Since the state of pixel formation sometimes differs between the edge portion and center portion of pixels 65, then dummy portion 70 is provided to eliminate such difference. Dummy portion 70 generally has an element width of 5 to 10 pixels. For example, dummy portion 70 has dummy photodiodes D1 –D6 as shown in FIG. 14(a). Since no output signals from the dummy portion are needed, it is covered with a photo-shielding member. However, in many cases, photodiodes may not be formed at the edge of dummy portion 70.
A third problem is caused by dark currents. Conventional solid-state imaging devices have been arranged to produce output charges of even-numbered pixels in succession to those of odd-numbered pixels. However, dummy portion 70 produces undesired charges (D1), (D2), and (D3) due to dark currents as shown in FIG. 14(a), though they are small. Hence, when it is attempted to read even-numbered pixels, e.g. charges (P2), (P4), and (P6) of photodiodes P2, P4, and P6, at time period t1 as shown in FIG. 14(b), these desired charges are added up together with undesired charges (D1), (D3), and (D5) of photodiode D1, D3, and D5, so that charges of photodiodes P2, P4, and P6 become (D1+P2), (D3+P4), and (D5+P6) as indicated at time period t2, respectively. Consequently, output signals of photodiodes P2, P4, and P6 become greater by (D1), (D3), and (D5), respectively, than desired values to produce horizontal stripes in the picture when arranged with those of odd-numbered pixels side by side. Further, even in a configuration in which dummy portion 70 includes no photodiodes, undesired charges due to some dark currents are observed, and thus it has been impossible to solve the problem of horizontal stripes appearing in the picture.
FIG. 15 shows changes of dark currents in charge memories 66 and 67 with the laps of time. With use of conventional FIT-CCD included, occurrence of undesired dark currents due to thermal excitation or the like has been unavoidable. Moreover, with the use of MFIT-CCD in progressive scan, appearance of undesired effect of dark currents in the picture becomes more conspicuous. Since the dark current increases with the stored time period of charges, the closer to pixel portion 65 pixels are located, the greater becomes the value of the dark current, and hence the larger undesired charges stored. As understood also from FIG. 15, the value of the dark current is smaller in odd-numbered pixels than that in even-numbered pixels, because the stored time in odd-numbered pixels is shorter than that in even-numbered pixels. Therefore, the problem in this case, like the first and second problems mentioned above, has resulted in occurrence of undesired horizontal stripes in the picture, when outputs in progressive scan are rearranged in integral-numeric order.